1. Field of the Invention
This invention relates to a liquid crystal display, and more particularly to a liquid crystal display device and a driving method thereof that prevents gravity degradation to thereby improve picture quality.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) controls the light transmittance of a liquid crystal using an electric field to display a picture. The LCD includes a liquid crystal display panel having liquid crystal cells arranged in a matrix, and a driving circuit for driving the liquid crystal display panel.
In the liquid crystal display panel, gate lines and data lines are arranged such that the gate lines and the data lines cross each other. The liquid crystal cell is positioned at each area where the gate lines cross the data lines. The liquid crystal display panel is provided with a pixel electrode and a common electrode for applying an electric field to each of the liquid crystal cells. Each pixel electrode is connected, via source and drain electrodes of a thin film transistor as a switching device, to any one of the data lines. The gate electrode of the thin film transistor is connected to any one of the gate lines thereby allowing the application of a pixel voltage signal to the pixel electrodes for each line.
The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for controlling the gate driver and the data driver, and a power supply for supplying various driving voltages used in the LCD. The timing controller controls a driving timing of the gate driver and the data driver and applies a pixel data signal to the data driver. The power supply generates driving voltages such as a common voltage VCOM, a gate high voltage VGH and a gate low voltage VGL, etc. The gate driver sequentially applies a scanning signal to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal display panel line by line. The data driver applies a data voltage signal to each of the data lines when the scanning signal is applied to one of the gate lines. Accordingly, the LCD controls the light transmittance by an electric field applied between the pixel electrode and the common electrode in response to the pixel voltage signal for each liquid crystal cell, thereby displaying a picture.
The data driver and the gate driver directly connected to the liquid crystal display panel integrate into a plurality of integrated circuits (IC's). Each of the integrated data drive IC's and gate drive IC's mount in a tape carrier package (TCP) and connect to the liquid crystal display panel by a tape automated bonding (TAB) system. In addition, the integrated data drive IC's and gate drive IC's may mount onto the liquid crystal display panel using a chip on glass (COG) system.
Herein, the drive IC's connected, via the TCP, to the liquid crystal display panel by the TAB system receives control signals and driving voltages input from the exterior over signal lines provided on a printed circuit board (PCB) connected to the TCP. In addition, the data drive IC's are connected, in series via signal lines provided on the data PCB, to each other, and commonly receive control signals and a pixel data signal from the timing control signal and driving voltages from the power supply. The gate drive IC's are connected, in series via signal lines provided on the gate PCB, and commonly receive control signals from the timing controller and driving voltages from the power supply.
The drive IC's mounted onto the liquid crystal display panel by the COG system are connected to each other by a line on glass (LOG) system in which signal lines are mounted on the liquid crystal display panel (i.e., a lower glass substrate) and receive control signals and driving voltages from the timing controller and the power supply.
Commonly, when the drive IC's are connected to the liquid crystal display panel by the TAB system, a LOG system is adopted to eliminate the PCB, thereby permitting the manufacturing of thin liquid crystal displays. Particularly, the gate drive IC's require relatively small signal lines. The small signal lines are provided on the liquid crystal display panel by the LOG system and thereby eliminate the gate PCB. Thus, the gate drive IC's of a TAB system are connected, in series, to each other over signal lines mounted on the lower glass substrate of the liquid crystal display panel. The gate drive IC's commonly receive control signals and driving voltage signals, which are hereinafter referred to as “gate driving signals”.
For instance, as shown in FIG. 1, a liquid crystal display omitting a gate PCB by utilizing LOG-type signal lines includes a liquid crystal display panel 1 and a plurality of data TCP's 8 connected between the liquid crystal display panel 1 and a data PCB 12. The liquid crystal display also includes a plurality of gate TCP's connected to other side of the liquid crystal display panel 1, data drive IC's 10 mounted in the data TCP's 8, and gate drive IC's 16 mounted in the gate TCP's 14.
The liquid crystal display panel 1 includes a lower substrate 2 provided with various signal lines and a thin film transistor array, an upper substrate 4 provided with a color filter array, and a liquid crystal injected between the lower substrate 2 and the upper substrate 4. The liquid crystal display panel 1 has a picture display area 21 consisting of liquid crystal cells provided at intersections between gate lines 20 and data lines 18 in order to display a picture. At the outer area of the lower substrate 2 located at the outer side of the picture display area 21, data pads extending from the data lines 18 and gate pads extending from the gate lines 20 are positioned. Further, a LOG-type signal line group 26 for transferring gate driving signals applied to the gate drive IC 16 is positioned at the outer area of the lower substrate 2.
The data TCP 8 is mounted with the data drive IC 10, and is provided with input pads 24 and output pads 25 electrically connected to the data drive IC 10. The input pads 24 of the data TCP 8 are electrically connected to the output pads of the data PCB 12 while the output pads 25 are electrically connected to the data pads on the lower substrate 2. Particularly, the first data TCP 8 is further provided with a gate driving signal transmission line group 22 electrically connected to the LOG-type signal line group 26 on the lower substrate 2. The gate driving signal transmission line group 22 applies gate driving signals from the timing controller and the power supply, via the data PCB 12, to the LOG-type signal line group 26.
The data drive IC's 10 convert digital pixel data signals into analog pixel voltage signals and applies the analog voltage signals to the data lines 18 on the liquid crystal display panel.
Similarly, a gate drive IC 16 is mounted on the gate TCP 14, and is provided with a gate driving signal transmission line group 28 electrically connected to the gate drive IC 16 and output pads 30. The gate driving signal transmission line group 28 is electrically connected to the LOG-type signal line group 26 on the lower substrate 2 while the output pads 30 are electrically connected to the gate pads on the lower substrate 2.
Each gate drive IC 16 sequentially applies a scanning signal such as a gate high voltage signal VGH during an interval to a gate line 20 in response to input control signals. Further, the gate drive IC 16 applies a gate low voltage signal Vgl to the gate line 20 in an interval other than the interval supplied where the gate high voltage signal VGH is supplied.
The LOG-type signal line group 26 usually includes signal lines that supply driving voltage signals from the power supply, such as a gate high voltage signal VGH and a gate low voltage signal VGL. The LOG-type signal line group 26 also includes a common voltage signal VCOM, a ground voltage signal GND and a supply voltage signal VCC. Furthermore, the LOG-type signal line group 26 has gate control signals from the timing controller, such as a gate start pulse GSP, a gate shift clock signal GSC and a gate enable signal GOE. The LOG-type signal line group 26 further includes a common line LVCOM for supplying a common voltage VCOM.
A LOG-type common line LVCOM is arranged, in parallel, in a fine pattern in a very confined narrow space like a pad portion positioned at an outer area of a picture display part 21. The LOG-type common line LVCOM is formed from a gate metal layer similar to the gate lines 20. A metal such as AlNd having a relatively large resistivity of 0.046 is usually used as the gate metal. As the LOG-type signal common line LVCOM is formed in a fine pattern within a confined area and is made from a gate metal having a relatively large resistivity value, the LOG-type signal common line LVCOM has a greater resistance than the signal lines formed from a copper film at an existent gate PCB. Because a resistance value of the LOG-type common line LVCOM is in proportion to a line length, a line resistance value increases as the LOG-type common line LVCOM extends away from the data PCB 12, thereby attenuating a gate driving signal. As a result, the common voltage VCOM transferred over the LOG-type common line LVCOM is distorted due to its line voltage value, thereby causing picture quality deterioration of a picture displayed on the picture display part 21.
This will be described in detail with reference to FIG. 2 below.
Referring to FIG. 2, a LOG-type common line LVCOM of a related art LCD is included in the LOG-type signal line group 26. The LOG-type common line LVCOM comprises a first LOG-type common line 50 provided at one edge of the liquid crystal display panel, and a second LOG-type common line 51 provided which intervenes with the first LOG-type common line 50 at the picture display area 21. The first LOG-type common line 50 consists of third to sixth LOG-type common lines 50a to 50d connected between a first data TCP 8 and the respective first to fourth gate TCP's 14A to 14D. When a liquid crystal in an in-plane switch (IPS) mode is driven with a horizontal electric field, the LOG-type common line LVCOM further includes a dummy common line 53 connected to the third to sixth LOG-type common lines 50a to 50d and to a common electrode (not shown) provided at the pixel area. On the other hand, when a liquid crystal in a twisted nematic (TN) mode is driven with a vertical electric field, the LOG-type common line LVCOM is connected to the common electrode provided at the upper substrate by a silver dot (not shown).
The third to sixth LOG-type common lines 50a to 50d have line voltage values a, b, c and d proportional to their line lengths. In addition, the third to sixth LOG-type common lines 50a to 50d are connected, via the first to fourth gate TCP's 14A to 14D, to each other in series.
In other words, the gate drive IC 16 mounted in the first gate TCP 14A is supplied with a first common voltage VCOM1 voltage-dropped in proportion to the first line resistance value a of the third LOG-type common line 50a. The first common voltage VCOM1 is applied, via the first gate drive IC 16, to common electrodes at a first horizontal line block A.
The gate drive IC 16 mounted in the second gate TCP 14B is supplied with a second common voltage VCOM2 voltage-dropped in proportion to the second line resistance value a+b of the third LOG-type common line 50a and the fourth LOG-type common line 50b connected to each other in series. The second common voltage VCOM2 is applied, via the second gate drive IC 16, to common electrodes at a second horizontal line block B.
The gate drive IC 16 mounted in the third gate TCP 14C is supplied with a third common voltage VCOM3 voltage-dropped in proportion to the third line resistance value a+b+c of the third to fifth LOG-type common line 50a to 50c connected to each other in series; The third common voltage VCOM3 is applied, via the third gate drive IC 16, to common electrodes at a third horizontal line block C.
The gate drive IC 16 mounted in the fourth gate TCP 14D is supplied with a fourth common voltage VCOM4 voltage-dropped in proportion to the fourth line resistance value a+b+c+d of the third to sixth LOG-type common line 50a to 50d connected to each other in series. The fourth common voltage VCOM4 is applied, via the fourth gate drive IC 16, to common electrodes at a fourth horizontal line block D. Particularly, as it goes from the first gate driving IC 16 toward the fourth gate driving IC 16, line resistance values a, b, c and d of the first and second LOG-type common lines 51 and 52 are added to each other, thereby resulting in the first to fourth common voltages VCOM1 to VCOM4 applied to the horizontal line blocks A to D having a relationship of VCOM1>VCOM2>VCOM3>VCOM4.
As the common voltages VCOM1 to VCOM4 supplied to the common electrodes are differentiated for each gate drive IC 16 in that manner, a brightness difference is generated among the horizontal line blocks A to D connected to different gate drive IC's 16. The brightness difference among the horizontal line blocks A to D results in horizontal brightness bands that cause a deterioration of picture quality.